1. Field of the Invention
The present invention relates to a method for erasing an electrically erasable nonvolatile memory device, and more in particular to a method for erasing an EEPROM-FLASH nonvolatile memory device.
The present invention moreover relates to an electrically erasable nonvolatile memory device, and more in particular to an EEPROM-FLASH nonvolatile memory device.
2. Description of the Related Art
As is known, nonvolatile memories comprise a memory array formed by memory cells arranged in rows and columns, in which word lines connect the gate terminals of the memory cells arranged on the same row, and bit lines connect the drain terminals of the memory cells arranged on the same column. Individual lines of the memory array are then addressed by means of a row decoder receiving an encoded address at input.
It is also known that in a floating-gate nonvolatile memory cell, storage of a logic state is performed by programming the threshold voltage of the memory cell itself through the definition of the amount of electrical charge stored in the floating-gate region.
According to the information stored, memory cells are distinguished into erased memory cells (logic state stored “1”), in the floating-gate region of which no electrical charge is stored, and written or programmed memory cells (logic state stored “0”), in the floating-gate regions of which an electrical charge is stored which is sufficient to cause a sensible increase in the threshold voltage of the memory cells themselves.
In nonvolatile memories, moreover, the memory array is generally divided into sectors, each of which is formed by a group of memory cells on which it is possible to perform the same operation simultaneously, generally an erase operation. In particular, in nonvolatile memories organized according to sectors it is possible to carry out reading and programming of individual memory cells of a sector and simultaneous erasing of all the memory cells of the sector, the latter operation being rendered possible by the fact that the memory cells belonging to the same sector have source terminals connected together.
In the panorama of nonvolatile memories, EEPROM memories are the ones that afford maximum flexibility of use in so far as they enable programming or erasing to be performed at the level of the individual byte, thanks to the fact that the memory cell is integrated with a selection transistor. The selection transistor is, however, cumbersome and, in practice, prevents this type of memories from reaching a storage capacity of the order of megabits.
For larger storage capacities the market has thus witnessed a considerable spread of EEPROM-FLASH memories, in which programming can again be performed at the level of the individual byte, but erasing can only be performed in blocks, the size range of which can be extremely wide, from 512 kbit to 1 Mbit, according to the needs of the user, and in any case cannot be lower than thousands of bits because otherwise the advantage, in terms of area, which distinguishes EEPROM-FLASH memories from EEPROM memories would be lost.
Within the family of EEPROM-FLASH memories, the two main architectures used are represented by the so-called NOR architecture and the so-called NAND architecture. In particular, the former architecture affords better performance than the latter in terms of reading speed, whilst the latter offers a better performance than the former in terms of erasing and programming speed.
The table below summarizes a comparison between the performance of EEPROM-FLASH memories with NOR architecture and the performance of EEPROM-FLASH memories with NAND architecture.
NANDNORProgramming0.4μs/byte6μs/byteErasing2ms/sector0.8ms/sectorRandom reading10μs130nsSector128kbit1Mbit
In particular, thanks to the short programming and erasing time, EEPROM-FLASH memories with a NAND architecture are particularly suited to meeting the requirements of portable applications, such as MP3 players and digital photocameras.
In order to compete also in these emerging market sectors, EEPROM-FLASH memories with NOR architecture are currently undergoing a revision of their traditional specifications; in particular, in-depth studies are in progress aimed at reducing the erase time.
As is known, erase of a nonvolatile memory is carried out by sectors and is a cumulative operation; i.e., it acts simultaneously and indistinctly on all the memory cells of the sector. Furthermore, it is a very complex operation in so far as it not only requires a number of preparative steps prior to erase proper, during which the electrical charges present in the floating-gate regions are extracted, and consequently the threshold voltage of the memory cells themselves is reduced, but also entails verifications and possible modifications subsequent to the erase proper in the event of the result of the erase not being fully satisfactory.
In particular, in order to erase a sector, first of all a pre-conditioning operation, also known as “program-all-0”, is performed, whereby all the memory cells of the sector are brought to the programmed state irrespective of their current state. This is due to the fact that if a sector were to be erased where some of the memory cells are written but others are already erased, during the erase step there would occur over-erase of the memory cells already erased, and the said cells, with all likelihood, would become depleted memory cells, i.e., memory cells having a negative threshold voltage, and hence ones draining a current even when their gate terminals are set at ground voltage. These cells are particularly troublesome in so far as they simulate the constant presence of erased memory cells on the columns to which they belong, and consequently cause all the memory cells belonging to said columns to be read as erased irrespective of their actual state.
In order to prevent this phenomenon from occurring and in order to yield the history of all the memory cells belonging to the same sector uniform, the procedure is to write the entire sector.
Following upon the preconditioning operation, all the memory cells of the sector are hence found to be programmed and present threshold voltages having the distribution illustrated in FIG. 1 and identified with the binary information “0” associated thereto. For the said distribution, in FIG. 1 there is moreover indicated the minimum value PV typical of threshold voltages, which is typically 5 V.
Subsequently, the erase step proper is carried out, during which the electrical charges present in the floating-gate regions are extracted, and consequently the threshold voltage of the memory cells themselves is reduced.
To do this, between the source terminal and the gate terminal of each memory cell a high electrical field is applied, such as to enable the electrons to abandon the floating-gate regions thanks to the so-called Fowler-Nordheim tunnel effect.
Application of the electrical potentials necessary for extracting the electrical charges from the floating-gate regions may be done in various ways. One of the methodologies that can, for example, be used for extraction of electrical charges from the floating-gate regions is known in the literature as of “erase with negative gate” and basically envisages leaving the drain terminal of the memory cell that is to be erased floating and applying to the gate terminal a negative voltage pulse typically having an amplitude of 10 V and a time duration in the region of 10 ms, and applying to the source terminal and body terminal a succession of voltage pulses the amplitude of which varies in stepwise fashion from a minimum value of 3 V to a maximum value of 8 V, with 300-mV step amplitude.
At the end of the erase pulse, a verification operation is carried out on all the memory cells of the sector to check the values of their threshold voltages, and this verification is performed by carrying out a margined reading which is able to guarantee correct recognition of the memory cell in the normal read mode.
In particular, the verification operation scans all the memory cells of the sector and is interrupted whenever a memory cell that does not pass the test is found. At this point, the next erase pulse is applied.
Consequently, the erase step proceeds with the application of an erase pulse followed by a verification step until all the memory cells have threshold voltages lower than a reference threshold voltage, which is the threshold voltage of the reference memory cells used during the verification operation.
Once the voltage pulses applied to the source and body terminals have reached their maximum amplitude, if the memory cells of the sector are not yet found to be all erased, then a second step of purely electrical erase is envisaged, during which both the gate terminals and the source and body terminals of the memory cells of the sector there are applied further erase pulses, up to a maximum of N pulses, in which the amplitude of the pulses applied to the source and body terminals of the memory cells is equal to the maximum amplitude envisaged.
FIG. 2 represents the biasing of the gate terminal (G), drain terminal (D), source terminal (S), and body terminal (B) of a flash memory cell during erase with negative gate, in which −VGE designates the negative voltage pulse applied to the gate terminal, and VBODY designates the succession of voltage pulses, the amplitude of which varies in step-like fashion, which are applied to the source and body terminals, whilst FIG. 3 is a flowchart illustrating the operations implemented during erase with negative gate.
At the end of the purely electrical erase step, all the memory cells of the sector have threshold voltages with the distribution illustrated in FIG. 4 and identified with the binary information “1” associated thereto, namely, a distribution presenting a substantially Gaussian form to which a “tail” is superimposed that is due to the depleted memory cells. In FIG. 4, moreover, EV (Erase Verify) designates the threshold voltage used during the verification operations referred to above, typically 2.5 V, whilst DV (Depletion Verify) designates the threshold voltage below which the memory cells are considered depleted, typically in the region of 1 V (i.e., higher than ground voltage in order to ensure reliability).
Merely for reasons of comparison, FIG. 4 moreover shows the distribution of the threshold voltages of the programmed memory cells shown in FIG. 1.
The sector erase step cannot, however, be considered concluded yet because it is still necessary to make sure that there are no depleted memory cells present which might give rise to errors during the reading step. As has been said previously, in fact, since the said memory cells have a negative threshold voltage and hence drain a current even when their gate terminals are set at ground voltage, they are particularly troublesome in so far as they simulate the constant presence of erased memory cells on the columns to which they belong, and consequently cause all the memory cells belonging to the said columns to be read as erased irrespective of their actual state.
Consequently, the erase step proper is followed by a step of search for depleted memory cells, also known as “soft-program” step, in which the presence is verified of a leakage current on the columns of the memory array, by biasing all the rows of the array at ground voltage.
When a column presenting this anomaly is identified, then the first memory cell of the column is addressed, and a programming pulse having a pre-set amplitude is applied to its gate terminal in order to shift the threshold of the memory cell slightly without, however, exceeding the value EV referred to above. Next, the second memory cell of the same column is read. If no leakage current is present in the memory cell, this means that the depleted cell was the previous one, which has already been recovered; otherwise, the memory cell considered is programmed, and so forth up to the end of the column.
When the end of the column is reached, the verification operation is repeated and, in the case where a leakage current is still present, the procedure described above is repeated, increasing, however, the amplitude of the programming pulse applied to the gate terminal of the memory cells during programming.
In conclusion, it may be recalled that the time interval of one second, which is typically used by a commercially available EEPROM-FLASH memory for erasing a 1-Mbit sector, may be evenly divided between the three basic operations: preconditioning, electrical erase, and soft-programming.
In the light of what has been said previously, it should be clear how the operation of purely electrical erase does not terminate until all the memory cells have a threshold voltage lower than EV.
In order to understand the impact on the erase time of this procedure, it is necessary to follow the displacements of the distribution of the threshold voltages of the memory cells during the step of purely electrical erase.
In particular, after a few erase pulses, the distribution of the threshold voltage of the memory cells assumes its final form and from that moment on just translates rigidly at each subsequent pulse.
By way of example, FIG. 5 illustrates the distributions of the threshold voltages of the erased memory cells after three erase pulses (curve A), after six erase pulses (curve B), and after nine erase pulses (curve C) in a given Flash process.
On account of the small geometrical differences between the various memory cells, in addition to the differences in the thickness of the oxides, amongst the memory cells erased there are some that are slower than others to erase; consequently, the actual distribution of the threshold voltages of the memory cells erased is of the type shown in FIG. 6, where, alongside the usual Gaussian, the presence may be noted of some isolated memory cells, indicated with dots, numbering three in the example illustrated.
It may therefore be readily understood how, in the presence of memory cells that erase more slowly, erase with negative gate, and more generally erase performed with any other method, proceeds with the application of erase pulses until also the last memory cell has a threshold voltage lower than EV, thus giving rise to a distribution of the threshold voltages of the erased memory cells of the type shown in FIG. 7.
In particular, on account of the memory cells that erase more slowly, the distribution of the threshold voltages of the memory cells continues to shift towards increasingly lower values, thus causing an increase in the number of memory cells to which a programming pulse will have to be applied during the soft-programming step, with evident negative effects on the time required for erasing the sector.